MOTOROLA
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by MCM6726D/D
SEMICONDUCTOR TECHNICAL DATA
128K x 8 Bit Fast Static Random
Access Memory
The MCM6726D is a 1,048,576 bit static random access memory organized
as 131,072 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
This device meets JEDEC standards for functionality and revolutionary pinout,
and is available in a 400 mil plastic small–outline J–leaded package.
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•
•
•
•
•
Single 5 V ± 10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: 8, 10, 12 ns
Center Power and I/O Pins for Reduced Noise
MCM6726D
WJ PACKAGE
400 MIL SOJ
CASE 857A–02
PIN ASSIGNMENT
A
A
A
30
A
4
29
A
5
28
G
6
27
DQ
7
26
DQ
VCC
8
25
VSS
VSS
9
24
VCC
DQ
10
23
DQ
11
22
DQ
W
12
21
A
A
MEMORY
MATRIX
512 ROWS x 256 x 8
COLUMNS
ROW
DECODER
3
DQ
A
A
DQ
A
31
DQ
VCC
VSS
2
E
A
A
A
A
32
A
BLOCK DIAGRAM
1
A
13
20
A
A
14
19
A
A
A
15
18
A
A
A
16
17
A
A
DQ
COLUMN I/O
COLUMN DECODER
INPUT
DATA
CONTROL
DQ
E
A
A
A
A
A
A
PIN NAMES
A
A
A . . . . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ . . . . . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
W
G
10/9/96
© Motorola, Inc. 1996
MOTOROLA FAST SRAM
MCM6726D
1
