MOTOROLA
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by MCM67B618B/D
SEMICONDUCTOR TECHNICAL DATA
Advance Information
MCM67B618B
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
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Single 5 V ±5% Power Supply
Fast Access Time: 9 ns Max
Byte Writeable via Dual Write Enables
Internal Input Registers (Address, Data, Control)
Internally Self–Timed Write Cycle
ADSP, ADSC, and ADV Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
3.3 V I/O Compatible
High Board Density 52–Lead PLCC Package
FN PACKAGE
PLASTIC
CASE 778–02
A6
A7
E
UW
LW
ADSC
ADSP
ADV
K
G
A8
A9
A10
PIN ASSIGNMENTS
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
42
12
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
DQ8
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
A5
A4
A3
A2
A1
A0
VSS
VCC
A15
A14
A13
A12
A11
The MCM67B618B is a 1,179,648–bit synchronous fast static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486™ and Pentiumr microprocessors. The MCM67B618B (organized as
65,536 words by 18 bits) is fabricated using Motorola’s high–performance
silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit
counter, high speed SRAM, and high drive capability outputs onto a single
monolithic circuit for reduced parts count implementation of cache data RAM
applications. Synchronous design allows precise cycle control with the use of an
external clock (K). BiCMOS circuitry reduces the overall power consumption of
the integrated functions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals
except output enable (G) are clock (K) controlled through positive–
edge–triggered noninverting registers.
DQ9
Bursts can be initiated with either address status processor (ADSP)
DQ10
or address status cache controller (ADSC) input pins. Subsequent
VCC
burst addresses can be generated internally by the MCM67B618B
VSS
(burst sequence imitates that of the i486 and Pentium) and controlled
DQ11
by the burst address advance (ADV) input pin. The following pages proDQ12
vide more detailed information on burst controls.
DQ13
Write cycles are internally self–timed and are initiated by the rising
DQ14
edge of the clock (K) input. This feature eliminates complex off–chip
VSS
VCC
write pulse generation and provides increased flexibility for incoming
DQ15
signals.
DQ16
Dual write enables (LW and UW) are provided to allow individually
DQ17
writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW
controls DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory. See Figure 2 for applications information.
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . Processor Address Status
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . +5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be connected for proper operation of the device.
i486 is a trademark and Pentium is a registered trademark of Intel Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 3
9/21/99
© Motorola, Inc. 1999
MOTOROLA FAST SRAM
MCM67B618B
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