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by MTD20P06HDL/D
SEMICONDUCTOR TECHNICAL DATA
™ Data Sheet
HDTMOS E-FET ™
High Density Power FET
DPAK for Surface Mount
Designer's
MTD20P06HDL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
15 AMPERES
60 VOLTS
RDS(on) = 175 MΩ
P–Channel Enhancement–Mode Silicon Gate
This advanced high–cell density HDTMOS E–FET is designed to
withstand high energy in the avalanche and commutation modes.
The new energy efficient design also offers a drain–to–source
diode with a fast recovery time. Designed for low–voltage,
high–speed switching applications in power supplies, converters
and PWM motor controls, and other inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.
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Ultra Low RDS(on), High–Cell Density, HDTMOS
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Avalanche Energy Specified
Surface Mount Package Available in 16 mm, 13–inch/2500
Unit, Tape & Reel, Add T4 Suffix to Part Number
™
D
G
CASE 369A–13, Style 2
DPAK
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–Source Voltage
Rating
VDSS
60
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
60
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 15
± 20
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
15
9.0
45
Adc
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C (1)
PD
72
0.58
1.75
Watts
W/°C
Watts
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 15 Apk, L = 2.7 mH, RG = 25 Ω)
EAS
300
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
1.73
100
71.4
°C/W
TL
260
°C
Operating and Storage Temperature Range
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Apk
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and HDTMOS are trademarks of Motorola Inc.
TMOS is a registered trademark of Motorola Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
©Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1995
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