Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in
a plastic envelope.
The device is intended for use in
Automotive applications, Switched
Mode Power Supplies (SMPS),
motor control, welding, DC/DC and
AC/DC converters, and in general
purpose switching applications.
PINNING - TO220AB
PIN
BUK555-60H
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
VGS = 5 V
PIN CONFIGURATION
MAX.
UNIT
60
41
125
175
38
V
A
W
˚C
mΩ
SYMBOL
DESCRIPTION
d
tab
1
gate
2
drain
3
source
g
tab
drain
s
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
VDS
VDGR
±VGS
±VGSM
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source
voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
ID
ID
IDM
Ptot
Tstg
Tj
MIN.
MAX.
UNIT
RGS = 20 kΩ
tp ≤ 50 µs
-
60
60
15
20
V
V
V
V
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
- 55
-
41
29
164
125
175
175
A
A
A
W
˚C
˚C
CONDITIONS
TYP.
MAX.
UNIT
-
1.2
K/W
60
-
K/W
THERMAL RESISTANCES
SYMBOL
PARAMETER
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
Rth j-a
August 1994
1
Rev 1.000
