HY57V1294020
4Banks x 8M x 4Bit Synchronous DRAM
DESCRIPTION
The Hyundai HY57V1294020 is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory
applications which require large memory density and high bandwidth. HY57V1294020 is organized as 4banks of
8,388,608x4.
HY57V1294020 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2, or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.3±0.3V power supply
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4, 8 and Full Page for Sequential Burst
•
•
Data mask function by DQM
•
- 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Internal four banks operation
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V1294020TC-75
100MHz
HY57V1294020TC-10S
HY57V1294020LTC-75
133MHz
HY57V1294020LTC-8
100MHz
HY57V1294020LTC-10S
400mil 54pin TSOP II
100MHz
HY57V1294020LTC-10
LVTTL
125MHz
HY57V1294020LTC-10P
4Banks x 8Mbits
x4
100MHz
Package
100MHz
HY57V1294020TC-10
Interface
125MHz
HY57V1294020TC-10P
Organization
133MHz
HY57V1294020TC-8
Power
100MHz
Normal
Low Power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0/Apr.99
