HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
2.5 V 184-pin Registered DDR-I SDRAM Modules
256MB, 512MB &1GByte Modules
PC1600 & PC2100
Preliminary Datasheet revision 0.91
• 184-pin Registered 8-Byte Dual-In-Line
DDR-I SDRAM Module for PC and Server
main memory applications
• Auto Refresh (CBR) and Self Refresh
• One bank 32M × 72, 64M x 72, and two bank
64M x 72 and 128M × 72 organization
• Re-drive for all input signals using register
and PLL devices.
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E2PROM
• JEDEC standard Double Data Rate
Synchronous DRAMs (DDR-I SDRAM) with a
single + 2.5 V (± 0.2 V) power supply
• Jedec standard MO-206 form factor:
133.35 mm (nom.) × 43.18 mm (nom.) × 4.00
mm (max.)
(6,80 mm max. with stacked components)
• Built with 256Mbit DDR-I SDRAMs in 66Lead TSOPII package
• Jedec standard reference layout:
Raw Cards A, B and C
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• Gold plated contacts
• Performance:
-7
-8
Component Speed Grade
Module Speed Grade
PC2100
Unit
DDR266A DDR200
PC1600
fCK
Clock Frequency (max.) @ CL = 2.5
143
125
MHz
fCK
Clock Frequency (max.) @ CL = 2
133
100
MHz
Description
The HYS 72Dxx0x0GR are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs)
organized as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1GB). The memory array is
designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock
distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM
timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes
are programmed with configuration data and the second 128 bytes are available to the customer.
INFINEON Technologies
1
2002-09-10 (revision 0.91)
