KM44C4004C, KM44C4104C
KM44V4004C, KM44V4104C
CMOS DRAM
4M x 4Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4.194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K
Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this
family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version.
This 4Mx4 EDO DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as main memory unit for high level computer, microcomputer and personal computer.
FEATURES
• Extended Data Out Mode operation
• Part Identification
(Fast Page Mode with Extended Data Out)
• CAS-before-RAS refresh capability
- KM44C4004C/C-L (5V, 4K Ref.)
- KM44C4104C/C-L (5V, 2K Ref.)
- KM44V4004C/C-L (3.3V, 4K Ref.)
- KM44V4104C/C-L (3.3V, 2K Ref.)
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Active Power Dissipation
• Early Write or output enable controlled write
Unit : mW
3.3V
Speed
• JEDEC Standard pinout
5V
• Available in Plastic SOJ and TSOP(II) packages
4K
2K
4K
2K
• Single +5V±10% power supply (5V product)
-5
324
396
495
605
• Single +3.3V±0.3V power supply (3.3V product)
-6
288
360
440
550
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
VCC
C4004C
5V
V4004C
3.3V
64ms
5V
V4104C
Normal
4K
C4104C
Refresh
cycle
Refresh period
L-ver
RAS
CAS
W
Vcc
Vss
VBB Generator
Data in
128ms
Refresh Timer
3.3V
2K
Control
Clocks
32ms
Refresh Control
Refresh Counter
• Performance Range
Speed
tRAC
tCAC
tRC
tHPC
Remark
-5
50ns
15ns
84ns
20ns
5V/3.3V
-6
60ns
17ns
104ns
25ns
A0-A11
(A0 - A10) *1
A0 - A9
(A0 - A10) *1
Buffer
Row Decoder
Memory Array
4,194,304 x4
Cells
Row Address Buffer
5V/3.3V
Sense Amps & I/O
Part
NO.
DQ0
to
DQ3
Data out
Col. Address Buffer
Column Decoder
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Buffer
OE
