KM718V887
256Kx18 Synchronous SRAM
Document Title
256Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
Initial draft
May. 15. 1997
Preliminary
0.1
Modify power down cycle timing & Interleaved read timing,
Insert Note 4 at AC timing characteristics.
Change ISB1 value from 10mA to 30mA.
Change ISB2 value from 10mA to 20mA.
February. 11. 1998
Preliminary
0.2
Change Undershoot spec
from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2)
Add Overshoot spec 4.6V((pulse width ≤tCYC/2)
Change VIH max from 5.5V to V DD+0.5V
April. 14. 1998
Preliminary
0.3
Change ISB2 value from 20mA to 30mA.
Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V.
May 13. 1998
Preliminary
1.0
Final spec Release
May 15. 1998
Final
2.0
Add VDDQ Supply voltage( 2.5V )
Dec. 02. 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Dec. 1998
Rev. 2.0
