MC10175
Quint Latch
The MC10175 is a high speed, low power quint latch. It features five
D type latches with common reset and a common two–input clock.
Data is transferred on the negative edge of the clock and latched on the
positive edge. The two clock inputs are “OR”ed together.
Any change on the data input will be reflected at the outputs while
the clock is low. The outputs are latched on the positive transition of
the clock. While the clock is in the high state, a change in the
information present at the data inputs will not affect the output
information. The reset input is enabled only when the clock is in the
high state.
• PD = 400 mW typ/pkg (No Load)
• tpd = 2.5 ns typ (Data to Output)
• tr, tf = 2.0 ns typ (20%–80%)
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
PDIP–16
P SUFFIX
CASE 648
LOGIC DIAGRAM
D0 10
D
Q
MC10175L
AWLYYWW
14 Q0
MC10175P
AWLYYWW
1
C R
D1 12
D
Q
PLCC–20
FN SUFFIX
CASE 775
15 Q1
C R
D2 13
Q
2
Q2
Q
D
3
A
WL
YY
WW
1
10175
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
Q3
C R
DIP PIN ASSIGNMENT
D3
9
D
VCC1
D4 5
C0 6
C1 7
RESET 11
D
Q
C R
16
VCC2
2
15
Q1
Q3
3
14
Q0
Q4
4
13
D2
D4
5
12
D1
C0
6
11
RESET
C1
4
1
Q2
7
10
D0
VEE
C R
8
9
D3
Q4
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
TRUTH TABLE
D
C0
C1
Reset
Qn+1
L
H
X
X
X
X
L
L
H
X
H
X
L
L
X
H
X
H
X
X
L
L
H
H
L
H
Qn
Qn
L
L
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
25 Units / Rail
PDIP–16
25 Units / Rail
MC10175FN
1
CDIP–16
MC10175P
January, 2002 – Rev. 7
Shipping
MC10175L
© Semiconductor Components Industries, LLC, 2002
Package
PLCC–20
46 Units / Rail
Publication Order Number:
MC10175/D
