MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Binary Counter
MC10H016
The MC10H016 is a high–speed synchronous, presettable, cascadable
4–bit binary counter. It is useful for a large number of conversion, counting and
digital integration applications.
• Counting Frequency, 200 MHz Minimum
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
• Positive Edge Triggered
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
MAXIMUM RATINGS
Symbol
Rating
Unit
Power Supply (VCC = 0)
Characteristic
VEE
–8.0 to 0
Vdc
Input Voltage (VCC = 0)
VI
0 to VEE
Vdc
Iout
50
100
mA
TA
0 to +75
°C
Tstg
–55 to +150
–55 to +165
°C
Output Current — Continuous
— Surge
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0°
Characteristic
Power Supply Current
25°
75°
Symbol
Min
Max
Min
Max
Min
Max
Unit
VCC1
1
16
VCC2
IE
—
126
—
115
—
126
mA
Q1
2
15
Q2
Q0
3
14
Q3
TC
4
13
CP
Input Current High
All Except MR
Pin 12 MR
Input Current Low
µA
IinH
—
—
450
1190
—
—
265
700
—
—
265
700
IinL
0.5
—
0.5
—
0.3
—
µA
High Output Voltage
VOH
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Vdc
PE
5
12
MR
Low Output Voltage
VOL
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
CE
6
11
P3
High Input Voltage
VIH
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
VIL
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
PO
7
10
P2
VEE
8
9
P1
AC PARAMETERS
Propagation Delay
Clock to Q
Clock to TC
MR to Q
tpd
Set–up Time
Pn to Clock
CE or PE to Clock
tset
Hold Time
Clock to Pn
Clock to CE or PE
thold
Counting Frequency
ns
1.0
0.7
0.7
2.4
2.4
2.4
1.0
0.7
0.7
2.5
2.5
2.5
1.0
0.7
0.7
2.7
2.6
2.6
2.0
2.5
—
—
2.0
2.5
—
—
2.0
2.5
—
—
1.0
0.5
—
—
1.0
0.5
—
—
1.0
0.5
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
—
—
ns
TRUTH TABLE
ns
CE
fcount
200
—
200
—
200
—
tr
0.5
2.0
0.5
2.1
0.5
2.2
Fall Time
tf
0.5
2.0
0.5
2.1
0.5
2.2
ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.0 volts.
CP
Function
L
L
H
H
X
L
L
L
L
L
Z
Z
Z
Z
ZZ
X
ns
MR
L
H
L
H
X
MHz
Rise Time
PE
X
H
X
Load Parallel (Pn to Qn)
Load Parallel (Pn to Qn)
Count
Hold
Masters Respond;
Slaves Hold
Reset (Qn = LOW,
TC = HIGH)
Z = Clock Pulse (Low to High); ZZ = Clock Pulse (High to Low)
Features include assertion inputs and outputs on each
of the four master/slave counting flip–flops. Terminal
count is generated internally in a manner that allows
synchronous loading at nearly the speed of the basic
counter.
9/96
© Motorola, Inc. 1996
2–1
REV 6