TMS320C6745/6747
www.ti.com
SPRS377C – SEPTEMBER 2008 – REVISED NOVEMBER 2009
TMS320C6745/6747 Fixed/Floating-point Digital Signal Processor
Check for Samples: TMS320C6745/6747
1 TMS320C6745/6747 Fixed/Floating-point Digital Signal Processor
1.1
Features
• Highlights
– 300 or 200-MHz C674x VLIW DSP
– TMS320C674x Fixed/Floating-Point VLIW
DSP Core
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– 128K-Byte RAM Shared Memory (C6747
Only)
– Two External Memory Interfaces
– Three Configurable 16550 type UART
Modules
– LCD Controller (C6747 Only)
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
– Two Master/Slave Inter-Integrated Circuit
– One Host-Port Interface (HPI) (C6747 only)
– USB 1.1 OHCI (Host) With Integrated PHY
(USB1) (C6747 Only)
• Applications
– Industrial Control
– USB, Networking
– High-Speed Encoding
– Professional Audio
• Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
• 300 or 200-MHz C674x VLIW DSP
• C674x Instruction Set Features
– Superset of the C67x+™ and C64x+™ ISAs
– 2400/1800 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
• C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
– 1024K-Byte L2 ROM
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• TMS320C674x Fixed/Floating-Point VLIW DSP
Core
– Load-Store Architecture With Non-Aligned
Support
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
• Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
• Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal
Approximation (RSQRxP) Operations Per
Cycle
– Two Multiply Functional Units
• Mixed-Precision IEEE Floating Point
Multiply Supported up to:
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
– 2 SP x DP -> DP Every Three Clocks
– 2 DP x DP -> DP Every Four Clocks
• Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies per
Clock Cycle, and Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
• 128K-Byte RAM Shared Memory (C6747 Only)
• 3.3V LVCMOS IOs (except for USB interfaces)
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DSP/BIOS, TMS320C6000, C6000 are trademarks of Texas Instruments.
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright © 2008–2009, Texas Instruments Incorporated
ADVANCE INFORMATION
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