TC74VHCT125,126AF/AFN/AFT/AFK
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74VHCT125AF,TC74VHCT125AFN,TC74VHCT125AFT,TC74VHCT125AFK
TC74VHCT126AF,TC74VHCT126AFN,TC74VHCT126AFT,TC74VHCT126AFK
TC74VHCT125AF/AFN/AFT/AFK
TC74VHCT126AF/AFN/AFT/AFK
Quad Bus Buffer
Quad Bus Buffer
The TC74VHCT125A/126A are high speed CMOS QUAD BUS
BUFFERs fabricated with silicon gate C2MOS technology.
They achieve the high speed operation similar to equivalent
Bipolar Shottky TTL while maintaining the CMOS low power
dissipation.
The TC74VHCT125A requires the 3-state control input G to
be set high to place the output into the high impedance state,
whereas the TC74VHCT126A requires the control input G to be
set low to place the output into high impedance.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing
3.3 V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can
be applied to the input and output (Note) pins without regard to
the supply voltage. There structure prevents device detsruction
due to mismatched supply and input/output voltages such as
battery back up, hot board insertion, etc.
Note:
VCC = 0 V
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74VHCT125AF, TC74VHCT126AF
TC74VHCT125AFN, TC74VHCT126AFN
TC74VHCT125AFT, TC74VHCT126AFT
Features
•
High speed: tpd = 3.8 ns (typ.) at VCC = 5 V
•
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
•
Compatible with TTL inputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
•
•
Power down protection is provided on all inputs and outputs.
Balanced propagation delays: tpLH ∼ tpHL
−
•
Low noise: VOLP = 0.8 V (max)
•
Pin and function compatible with the 74 series
(74AC/HC/F/ALS/LS etc.) 125/126 types.
TC74VHCT125AFK, TC74VHCT126AFK
Weight
SOP14-P-300-1.27A:
SOL14-P-150-1.27:
TSSOP14-P-0044-0.65A:
VSSOP14-P-0030-0.50:
1
0.18 g (typ.)
0.12 g (typ.)
0.06 g (typ.)
0.02 g (typ.)
2008-12-01
