LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
General Description
The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to ’F74
data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
n Guaranteed 4000V minimum ESD protection.
See Section 0
Commercial
Military
Package
Number
N16E
Package Description
16-Lead (0.300" Wide) Molded Dual-in-Line
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74F109PC
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Ordering Code:
Features
54F109DM (Note 2)
16-Lead (0.150" Wide) Molded Small Outline,
JEDEC
M16D
16-Lead (0.300" Wide) Molded Small Outline,
EIAJ
W16A
16-Lead Cerpack
54F109LM (Note 2)
74F109SJ (Note 1)
16-Lead Ceramic Dual-in-Line
M16A
54F109FM (Note 2)
74F109SC (Note 1)
J16A
E20A
16-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB.
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Logic Symbols
DS009471-3
54F/74F109
54F/74F109
Dual JK Positive Edge-Triggered Flip-Flop
54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
November 1994
DSXXX
IEEE/IEC
DS009471-4
DS009471-6
FAST ® and TRI-STATE ® are registered trademarks of National Semiconductor Corporation.
© 1997 National Semiconductor Corporation
www.national.com
DS009471
PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1
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Logic Diagram
DS009471-5
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Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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