ST24LC21B, ST24LW21
ST24FC21, ST24FW21
1 Kbit (x8) Dual Mode Serial EEPROM
for VESA PLUG & PLAY
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
3.6V to 5.5V SINGLE SUPPLY VOLTAGE
HARDWARE WRITE CONTROL (ST24LW21
and ST24FW21)
TTL SCHMITT-TRIGGER on VCLK INPUT
100k / 400k Hz COMPATIBILITY with the I2C
BUS BIT TRANSFER RANGE
TWO WIRE SERIAL INTERFACE I2C BUS
COMPATIBLE
I2C PAGE WRITE (up to 8 Bytes)
I2C BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ERROR RECOVERY MECHANISM
(ST24FC21 and ST24FW21) VESA 2
COMPATIBLE
DESCRIPTION
The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are 1K bit electrically erasable programmable memory (EEPROM), organized in
128x8 bits. In the text, products are referred as
ST24xy21, where "x" is either "L" for VESA 1 or "F"
for VESA 2 compatible memories and where "y"
indicates the Write Control pin connection: "C"
means WC on pin 7 and "W" means WC on pin 3.
8
8
1
1
SO8 (M)
150mil Width
PSDIP8 (B)
0.25mm Frame
Figure 1. Logic Diagram
VCC
SCL
VCLK
SDA
ST24xy21
WC
Table 1. Signal Names
SDA
Serial Data Address Input/Output
SCL
Serial Clock (I2C mode)
VCC
Supply Voltage
VSS
Ground
VCLK
Clock Transmit only mode
WC
Write Control
VSS
AI01741
January 1999
Note: WC signal is only available for ST24LW21 and ST24FW21
products.
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ST24LC21B, ST24LW21, ST24FC21, ST24FW21
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature
–40 to 85
°C
TSTG
Storage Temperature
–65 to 150
°C
TLEAD
Lead Temperature, Soldering
215
260
°C
TA
VIO
40 sec
10 sec
Input or Output Voltages
VCC
(SO8 package)
(PSDIP8 package)
Supply Voltage
VESD
–0.3 to 6.5
–0.3 to 6.5
Electrostatic Discharge Voltage (Human Body model)
V
V
(2)
4000
500
Electrostatic Discharge Voltage (Machine model) (3)
V
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
Table 3. Device Select Code
Device Code
Chip Enable
RW
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Device Select
1
0
1
0
X
X
X
RW
Note: The MSB b7 is sent first.
X = 0 or 1.
DESCRIPTION (cont’d)
The ST24xy21 can operate in two modes: Transmit-Only mode and I2C bidirectional mode. When
powered, the device is in Transmit-Only mode with
EEPROM data clocked out from the rising edge of
the signal applied on VCLK.
The device will switch to the I2C bidirectional mode
upon the falling edge of the signal applied on SCL
pin. When in I2C mode, the ST24LC21B (or the
ST24LW21) cannot switch back to the Transmit
Only mode (except when the power supply is removed). For the ST24FC21 (or the ST24FW21),
after the falling edge of SCL, the memory enter in
a transition state which allowed to switch back to
the Transmit-Only mode if no valid I2C activity is
observed. The device operates with a power supply
value as low as +3.6V. Both Plastic Dual-in-Line
and Plastic Small Outline packages are available.
Transmit Only Mode
After a Power-up, the ST24xy21 is in the Transmit
Only mode. A proper initialization sequence (see
Figure 3) must supply nine clock pulses on the
VCLK pin (in order to internally synchronize the
device). During this initialization sequence, the
SDA pin is in high impedance. On the rising edge
of the tenth pulse applied on VCLK pin, the device
will output the first bit of byte located at address 00h
(most significant bit first).
A byte is clocked out (on SDA pin) with nine clock
pulses on VCLK: 8 clock pulses for the data byte
and one extra clock pulse for a Don’t Care bit.
As long as the SCL pin is held high, each byte of
the memory array is transmitted serially on the SDA
pin with an automatic address increment.
When the last byte is transmitted, the address
counter will roll-over to location 00h.
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