LF3320
LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
Horizontal Digital Image Filter
DEVICES INCORPORATED
FEATURES
DESCRIPTION
83 MHz Data Rate
12-bit Data or Coefficients (Expandable to 24-bit)
32-Tap FIR Filter, Cascadable for
More Filter Taps
Over 49 K-bits of on-board Memory
LF InterfaceTM Allows All 256 Coefficient Sets to be Updated Within
Vertical Blanking
Various Operating Modes: Dual
Filter, Single Filter, Double Wide
Data or Coefficient, Matrix Multiplication, and Accumulator Access.
Selectable 16-bit Data Output with
User-Defined Rounding and Limiting
Supports Interleaved Data Streams
Supports Decimation up to 16:1 for
Increasing Number of Filter Taps
3.3 Volt Supply
144 Lead PQFP
The LF3320 filters digital images in
the horizontal dimension at real-time
video rates. The input and coefficient
data are both 12 bits and in two’s complement format. The output is also in
two’s complement format and may be
rounded to 16 bits.
The LF3320 is designed to take advantage of symmetric coefficient sets.
When symmetric coefficient sets are
used, the device can be configured as
a single 32-tap FIR filter or as two separate 16-tap FIR filters.
Interleave/Decimation Registers (I/D
Registers) allow interleaved data to be
fed directly into the device and filtered without separating the data into
individual data streams.
The LF3320 can handle a maximum of
sixteen data sets interleaved together.
The I/D Registers and on-chip accumulators facilitate using decimation
to increase the number of filter taps.
Decimation of up to 16:1 is supported.
The LF3320 contains enough on-board
memory to store 256 coefficient sets.
Two separate LF InterfacesTM allow
all 256 coefficient sets to be updated
within vertical blanking.
When asymmetric coefficient sets are
used, the device can be configured
as a single 16-tap FIR filter or as
two separate 8-tap FIR filters. MulNOTE: loading registers via the LF
tiple LF3320s can be cascaded to create interface must not exceed 90MHz. The
larger filters.
PAUSE pin must be used to throttle
back the LF interface at clock speeds
above 90MHz.
LF3320 BLOCK DIAGRAM
ROUT11-0
DIN11-0
CAA7-0
12
12
INTERLEAVE / DECIMATION
REGISTERS
12
12
8
8
CENA
CFA11-0
PAUSEA
LDA
RIN11-0
COUT11-0
CAB7-0
CENB
12
256
COEFFICIENT
SET
STORAGE
16-TAP
FILTER A
16-TAP
FILTER B
256
COEFFICIENT
SET
STORAGE
12
CFB11-0
PAUSEB
LDB
ROUND
SELECT
LIMIT
CIRCUITRY
CLK
OED
16
DOUT15-0
Video Imaging Products
2-1
6/22/2007–LDS.3320-R
