CY7C1399BN
256-Kbit (32 K × 8) Static RAM
256-Kbit (32 K × 8) Static RAM
Features
Functional Description
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Temperature Ranges
❐ Industrial: –40 °C to 85 °C
❐ Commercial: 0 °C to 70 °C
❐ Automotive-A: –40 °C to 85 °C
The CY7C1399BN is a high-performance 3.3 V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE) and
active LOW Output Enable (OE) and tristate drivers. The device
has an automatic power-down feature, reducing the power
consumption by more than 95% when deselected.
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Single 3.3 V power supply
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Ideal for low-voltage cache memory applications
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High speed: 12 ns
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Low active power
❐ 180 mW (max)
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Low-power alpha immune 6T cell
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Available in pb-free and non pb-free plastic SOJ and TSOP- I
packages
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins is present
on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable (WE)
is HIGH. The CY7C1399BN is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
Logic Block Diagram
g
I/O0
INPUT BUFFER
I/O1
ROW DECODER
I/O2
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
32K x 8
ARRAY
I/O3
I/O4
I/O5
CE
WE
POWER
DOWN
COLUMN
DECODER
I/O7
•
A 14
A 12
A 13
A 11
A 10
OE
Cypress Semiconductor Corporation
Document Number: 001-06490 Rev. *F
I/O6
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 16, 2014
