Micrel, Inc.
DUAL CML/PECL/LVPECL-to-LVDS
TRANSLATOR
SuperLite™
SY55855V
SuperLite™
SY55855V
FEATURES
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Guaranteed fMAX >750MHz over temperature
1.5Gbps throughput capability
3.0V to 5.7V power supply
Guaranteed <700ps propagation delay over
temperature
Guaranteed <50ps within-device skew over
temperature
LVDS compatible outputs
Fully differential I/O architecture
Wide operating temperature range: –40°C to +85°C
Available in a tiny 10-pin MSOP package
SuperLite™
DESCRIPTION
The SY55855V is a fully differential, CML/PECL/
LVPECL-to-LVDS translator. It achieves LVDS signaling
up to 1.5Gbps, depending on the distance and the
characteristics of the media and noise coupling sources.
LVDS is intended to drive 50Ω impedance transmission
line media such as PCB traces, backplanes, or cables.
SY55855V inputs can be terminated with a single
resistor between the true and the complement pins of a
given input.
The SY55855V is a member of Micrel’s new
SuperLite™ family of high-speed logic devices. This family
features very small packaging, high signal integrity, and
operation at many different supply voltages.
FUNCTIONAL BLOCK DIAGRAM
D0
/Q0
D1
High-speed logic
Data communications systems
Wireless communications systems
Telecom systems
Q1
/D1
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Q0
/D0
APPLICATIONS
/Q1
SuperLite is a trademark of Micrel, Inc.
M9999-110705
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
1
Amendment: /0
Issue Date: November 2005
SuperLite™
SY55855V
Micrel, Inc.
FUNCTIONAL DESCRIPTION
unconnected. For VCC ≤ 3.0V, connect the complement input
to VCC and leave the true input unconnected. To make an
input static logic one, connect the true input to VCC, leave
the complement input unconnected. These are the only two
safe ways to cause inputs to be at a static value. In particular,
no input pin should be directly connected to ground. All NC
(no connect) pins should be unconnected.
Establishing Static Logic Inputs
The true pin of an input pair is internally biased to ground
through a 75kΩ resistor. The complement pin of an input
pair is internally biased halfway between VCC and ground
by a voltage divider consisting of two 75kΩ resistors. In this
way, unconnected inputs appear as logic zeros. To keep an
input at static logic zero at VCC > 3.0V, leave both inputs
VCC
X
NC
X
NC
/X
NC
/X
VCC > 3.0V
Figure 1. Hard Wiring a Logic “1” (1)
Note 1.
X is either D0 or D1 input. /X is either /D0 or /D1 input.
NC
X
VCC
/X
VCC ≤ 3.0V
Figure 2. Hard Wiring a Logic “0” (1)
Note 1.
M9999-110705
hbwhelp@micrel.com or (408) 955-1690
3
X is either D0 or D1 input. /X is either /D0 or /D1 input.
