TC74LVX138F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74LVX138F,TC74LVX138FN,TC74LVX138FT
3-to-8 Line Decoder
Note:
The TC74LVX138F/ FN/ FT is a high-speed CMOS 3-to-8 line
decoder fabricated with silicon gate CMOS technology. Designed
for use in 3-V systems, it achieves high-speed operation while
maintaining the CMOS low power dissipation.
This device is suitable for low-voltage and battery operated
systems.
When the device is enabled, 3 Binary Select inputs (A, B and
C) determine which one of the outputs ( Y 0 - Y7 ) will go low.
When enable input G1 is held low or either G 2 A or G2B is
held high, decoding function is inhibited and all outputs go high.
G1, G 2 A , and G2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
An input protection circuit ensures that 0 to 5.5V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5V to 3V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
•
xxxFN (JEDEC SOP) is not available in
Japan.
TC74LVX138F
TC74LVX138FN
TC74LVX138FT
High-speed: tpd = 5.5 ns (typ.) (VCC = 3.3 V)
•
Low power dissipation: ICC = 4 μA (max) (Ta = 25°C)
•
Input voltage level: VIL = 0.8 V (max) (VCC = 3 V)
VIH = 2.0 V (min) (VCC = 3 V)
•
•
Power-down protection provided on all inputs
∼
Balanced propagation delays: tpLH − tpHL
•
Pin and function compatible with 74HC138
Weight
SOP16-P-300-1.27A
SOL16-P-150-1.27
TSSOP16-P-0044-0.65A
1
: 0.18 g (typ.)
: 0.12 g (typ.)
: 0.06 g (typ.)
2007-10-17
