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CDCM61004
SCAS871H – FEBRUARY 2009 – REVISED JANUARY 2016
CDCM61004 Four Output, Integrated VCO, Low-Jitter Clock Generator
1 Features
2 Applications
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Low-Jitter Clock Driver for High-End Datacom
Applications Including SONET, Ethernet, Fibre
Channel, Serial ATA, and HDTV
Cost-Effective High-Frequency Crystal Oscillator
Replacement
3 Description
The CDCM61004 is a highly versatile, low-jitter
frequency synthesizer capable of generating four lowjitter clock outputs, selectable between low-voltage
positive emitter coupled logic (LVPECL), low-voltage
differential signaling (LVDS), or low-voltage
complementary
metal
oxide
semiconductor
(LVCMOS) outputs, from a low-frequency crystal of
LVCMOS input for a variety of wireline and data
communication applications. The CDCM61004
features an onboard PLL that can be easily
configured solely through control pins. The overall
output random jitter performance is less than 1 ps,
RMS (from 10 kHz to 20 MHz), making this device a
perfect choice for use in demanding applications such
as SONET, Ethernet, Fibre Channel, and SAN. The
CDCM61004 is available in a small, 32-pin,
5-mm × 5-mm VQFN package.
Device Information(1)
PART NUMBER
CDCM61004
PACKAGE
BODY SIZE (NOM)
VQFN (32)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
CDCM61004 Block Diagram
RSTN
PR[1...0]
2
OD[2...0]
3
CDCM61004
Output
Driver
VCO
Feedback
Divider
LVPECL/
LVCMOS/
LVDS
Output
Driver
LVPECL/
LVCMOS/
LVDS
Output
Driver
LVPECL/
LVCMOS/
LVDS
Output
Driver
PFD
Charge Pump
Loop Filter
Crystal/
LVCMOS
Output Divider
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One Crystal/LVCMOS Reference Input Including
24.8832 MHz, 25 MHz, and 26.5625 MHz
Input Frequency Range: 21.875 MHz to
28.47 MHz
On-Chip VCO Operates in Frequency Range of
1.75 GHz to 2.05 GHz
4x Output Available:
– Pin-Selectable Between LVPECL, LVDS, or
2-LVCMOS; Operates at 3.3 V
LVCMOS Bypass Output Available
Output Frequency Selectable by /1, /2, /3, /4, /6,
/8 from a Single Output Divider
Supports Common LVPECL/LVDS Output
Frequencies:
– 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
155.52 MHz, 156.25 MHz, 159.375 MHz,
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,
311.04 MHz, 312.5 MHz, 622.08 MHz,
625 MHz
Supports Common LVCMOS Output Frequencies:
– 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
155.52 MHz, 156.25 MHz, 159.375 MHz,
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz
Output Frequency Range: 43.75 MHz to
683.264 MHz (See Table 4)
Internal PLL Loop Bandwidth: 400 kHz
High-Performance PLL Core:
– Phase Noise typically at –146 dBc/Hz at
5-MHz Offset for 625-MHz LVPECL Output
– Random Jitter typically at 0.509 ps, RMS
( 10 kHz to 20 MHz) for 625-MHz LVPECL
Output
Output Duty Cycle Corrected to 50% (± 5%)
Low Output Skew of 30 ps on LVPECL Outputs
Divider Programming Using Control Pins:
– Two Pins for Prescaler/Feedback Divider
– Three Pins for Output Divider
– Two Pins for Output Select
Chip Enable Control Pin Available
3.3-V Core and I/O Power Supply
Industrial Temperature Range: –40°C to 85°C
5-mm × 5-mm, 32-pin, VQFN (RHB) Package
ESD Protection Exceeds 2 kV (HBM)
Prescaler
1
LVPECL/
LVCMOS/
LVDS
3.3 V
LVCMOS
CE
2
OS[1...0]
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
