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74LVXC3245TTR
74LVXC3245 OCTAL DUAL SUPPLY BUS TRANSCEIVER s s s s s s s HIGH SPEED: tPD = 8ns (MAX.) at TA=25°C VCCA = 3.3V, VCCB = 5.0V LOW POWER DISSIPATION: ICCA = ICCB = 5µA(MAX.) at TA=25°C LOW NOISE: VOLP =0.3V (TYP.) at VCCA=3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCCA(OPR) = 2.7V to 3.6V (1.2V Data Retention) VCCB(OPR) = 2.7V to 5.5V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES C3245 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVXC3245 is a dual supply 8 bit configurable low voltage CMOS OCTAL BUS TRANSCEIVER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Designed for use as an interface between a 3.3V bus and a 3.3V to 5V bus in a mixed 3.3V/5V supply systems, it achieves high speed operation while maintaining the CMOS low power dissipation. SOP TSSOP Table 1: Order Codes PACKAGE T&R SOP TSSOP 74LVXC3245MTR 74LVXC3245TTR This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated. The A-port interfaces with the 3V bus, the B-port with the 5V bus. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols August 2004 Rev. 4 1/14
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