SN74LVC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES219B – APRIL 1999 – REVISED FEBRUARY 2000
D
D
D
D
EPIC ™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Ioff Feature Supports Partial-Power-Down
Mode Operation
Supports 5-V VCC Operation
Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
DBV OR DCK PACKAGE
(TOP VIEW)
A
B
GND
1
5
VCC
4
Y
2
3
description
This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G32 performs the Boolean function Y
+ A ) B or Y + A • B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
PRODUCT PREVIEW
The SN74LVC1G32 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
B
OUTPUT
Y
H
X
H
X
H
H
L
L
L
A
logic symbol†
A
B
1
≥1
2
4
Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
A
B
1
2
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright © 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74LVC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES219B – APRIL 1999 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
1.9
IOH = –8 mA
IOH = –16 mA
VOH
3V
3.8
0.1
1.65 V
0.45
2.3 V
0.3
IOL = 16 mA
0.4
3V
IOL = 24 mA
IOL = 32 mA
VI = 5.5 V or GND
0.55
±5
mA
±10
mA
1.65 V to 5.5 V
10
mA
3 V to 5.5 V
500
mA
0 to 5.5 V
0
One input at VCC – 0.6 V,
V
0.55
4.5 V
VI or VO = 5.5 V
VI = 5.5 V or GND,
ICC
∆ICC
V
1.65 V to 5.5 V
IOL = 4 mA
IOL = 8 mA
A or B inputs
UNIT
2.3
4.5 V
IOH = –32 mA
IOL = 100 mA
II
Ioff
MAX
2.4
IOH = –24 mA
VOL
TYP†
VCC–0.1
1.2
2.3 V
IOH = –100 mA
IOH = –4 mA
MIN
IO = 0
Other inputs at VCC or GND
Ci
VI = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
3.3 V
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 4)
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
PARAMETER
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
Y
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
f = 10 MHz
POST OFFICE BOX 655303
VCC = 3.3 V
TYP
VCC = 5 V
TYP
UNIT
pF
• DALLAS, TEXAS 75265
3
PRODUCT PREVIEW
PARAMETER
