MC14094B
8−Stage Shift/Store Register
with Three−State Outputs
The MC14094B combines an 8−stage shift register with a data latch
for each stage and a 3−state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The QS output data is for use in
high−speed cascaded systems. The QS output data is shifted on the
following negative clock transition for use in low−speed cascaded
systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while
strobe is high.
Outputs of the eight data latches are controlled by 3−state buffers
which are placed in the high−impedance state by a logic Low on
Output Enable.
Features
• 3−State Outputs
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
16
MC14094BCP
AWLYYWWG
1
16
SOIC−16
D SUFFIX
CASE 751B
14094BG
AWLYWW
1
Schottky TTL Load Over the Rated Temperature Range
• Input Diode Protection
• Data Latch
• Dual Outputs for Data Out on Both Positive and
•
•
•
16
Negative Clock Transitions
Useful for Serial−to−Parallel Data Conversion
Pin−for−Pin Compatible with CD4094B
Pb−Free Packages are Available*
1
16
SOEIAJ−16
F SUFFIX
CASE 966
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
VDD
Parameter
Value
Unit
−0.5 to +18.0
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
MC14094B
ALYWG
1
V
−0.5 to VDD + 0.5
mW
Vin, Vout
Iin, Iout
DC Supply Voltage Range
14
094B
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
Input or Output Voltage Range
(DC or Transient)
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
TA
Ambient Temperature Range
−55 to +125
°C
ORDERING INFORMATION
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6
1
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Publication Order Number:
MC14094B/D
