SRAM
AS5C2568
Austin Semiconductor, Inc.
32K x 8 SRAM
PIN ASSIGNMENT
(Top View)
SRAM MEMORY ARRAY
28-PIN PSOJ (DJ)
FEATURES
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Access Times: 12, 15, & 20ns
Fast output enable (tDOE) for cache applications
Low active power: 400 mW (TYP)
Low power standby
Fully static operation, no clock or refresh required
High-performance, low-power CMOS double-metal process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\
All inputs and outputs are TTL compatible
OPTIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
MARKING
• Timing
12ns access*
15ns access
20ns access
-12
-15
-20
• Package(s)**
Plastic SOJ
DJ
• Operating Temperature Ranges
Military -55oC to +125oC
Industrial -40oC to +85oC
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5
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10
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12
13
14
28 VCC
27 WE\
26 A13
25 A8
24 A9
23 A11
22 OE\
21 A10
20 CE\
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
XT
IT
No. 906
GENERAL DESCRIPTION
* -12 available in IT only.
** For ceramic version of this product, see the MT5C2568
data sheet.
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs using a four-transistor
memory cell. These SRAMs are fabricated using double-layer
metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) and output enable
(OE\) capability. These enhancements can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW.
The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby
power requirements.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS5C2568
Rev. 2.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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