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74F544D
54F 74F544 Octal Registered Transceiver General Description Features The ’F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow The A outputs are guaranteed to sink 24 mA (20 mA Mil) while the B outputs are rated for 64 mA (48 mA Mil) The ’F544 inverts data in both directions Y Commercial Package Number Military 74F544SPC Y Y Y Y 8-bit octal transceiver Back-to-back registers for storage Separate controls for data flow in each direction A outputs sink 24 mA (20 mA Mil) B outputs sink 64 mA (48 mA Mil) 300 mil slim PDIP Package Description N24C 24-Lead (0 300 Wide) Molded Dual-In-Line 54F544DM (Note 2) J24A 24-Lead Ceramic Dual-In-Line 54F544SDM (Note 2) J24F 24-Lead (0 300 Wide) Ceramic Dual-In-Line 74F544SC (Note 1) M24B 24-Lead (0 300 Wide) Molded Small Outline JEDEC 74F544MSA (Note 1) MSA24 24-Lead Molded Shrink Small Outline EIAJ Type II 54F544FM (Note 2) W24C 24-Lead Cerpack 54F544LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX and MSAX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC TL F 9555 – 2 TL F 9555 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9555 RRD-B30M75 Printed in U S A 54F 74F544 Octal Registered Transceiver December 1994 Logic Diagram TL F 9555 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 3
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