IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET
DESCRIPTION:
FEATURES:
•
•
•
•
•
•
•
•
•
IDT54/74FCT273T/AT/CT
The FCT273T is an octal D flip-flop built using an advanced dual metal
CMOS technology. The FCT273T has eight edge-triggered D-type flipflops with individual D inputs and O outputs. The common buffered Clock
(CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the low-to-high clock transition, is transferred to the corresponding flip-flop’s O output.
All outputs will be forced low independently of Clock or Data inputs by
a low voltage level on the MR input. The device is useful for applications
where the true output only is required and the Clock and Master Reset are
common to all storage elements.
Std., A, and C grades
Low input and output leakage ≤1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
High Drive outputs (-15mA IOH, 48mA IOL)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
– Industrial: SOIC, SSOP, QSOP
– Military: CERDIP, LCC
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
CP
Q
D
Q
D
CP
CP
RD
Q
D
CP
RD
Q
D
Q
D
CP
RD
RD
Q
D
CP
CP
RD
Q
D
CP
RD
Q
D
CP
RD
RD
MR
O0
O1
O2
O3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
O4
O5
O6
O7
JUNE 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-2568/2
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10%
Symbol
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current(4)
VCC = Max.
VI = 2.7V
—
—
±1
µA
IIL
Input LOW Current(4)
VCC = Max.
VI = 0.5V
—
—
±1
II
Input HIGH Current(4)
VCC = Max., VI = VCC (Max.)
—
—
±1
µA
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
–60
2.4
–120
3.3
–225
—
mA
2
3
—
—
0.3
0.5
V
—
200
—
mV
—
0.01
1
mA
IOS
VOH
Parameter
Short Circuit Current
Output HIGH Voltage
VOL
Output LOW Voltage
VH
Quiescent Power Supply Current
IOH = –6mA MIL
IOH = –8mA IND
IOH = –12mA MIL
IOH = –15mA IND
IOL = 32mA MIL
IOL = 48mA IND
Input Hysteresis
ICC
VCC = Max., VO =
VCC = Min
VIN = VIH or VIL
GND(3)
VCC = Min
VIN = VIH or VIL
—
VCC = Max.
VIN = GND or VCC
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
3