MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input AND Gate
MC54/74HC08A
High–Performance Silicon–Gate CMOS
The MC54/74HC08A is identical in pinout to the LS08. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
1
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
14
Low Input Current: 1µA
1
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
1
D SUFFIX
SOIC PACKAGE
CASE 751A–03
1
Chip Complexity: 24 FETs or 6 Equivalent Gates
DT SUFFIX
TSSOP PACKAGE
CASE 948B–03
14
LOGIC DIAGRAM
14
A1
B1
A2
B2
A3
B3
A4
B4
1
3
2
Y1
ORDERING INFORMATION
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
4
6
5
Y2
Y = AB
9
8
10
Y3
FUNCTION TABLE
12
11
13
Inputs
Y4
Output
A
Pinout: 14–Lead Packages (Top View)
VCC
B4
A4
Y4
B3
A3
Y3
14
13
12
11
10
9
8
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2
GND
2/98
1
REV 7
B
Y
L
L
H
H
PIN 14 = VCC
PIN 7 = GND
© Motorola, Inc. 1998
Ceramic
Plastic
SOIC
TSSOP
L
H
L
H
L
L
L
H
MC54/74HC08A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
≤85°C
≤125°C
Unit
Parameter
VIH
Minimum High–Level Input Voltage
Vout = 0.1V or VCC –0.1V
|Iout| ≤ 20µA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low–Level Input Voltage
Vout = 0.1V or VCC – 0.1V
|Iout| ≤ 20µA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout| ≤ 20µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
VOH
Condition
–55 to 25°C
Symbol
Vin =VIH or VIL
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout| ≤ 20µA
Vin = VIH or VIL
Iin
ICC
|Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA
|Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
±0.1
±1.0
±1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0µA
6.0
1.0
10
40
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
Symbol
Guaranteed Limit
VCC
V
Parameter
–55 to 25°C
≤85°C
≤125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
Maximum Input Capacitance
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
Power Di i i C
P
Dissipation Capacitance (P B ff )*
i
(Per Buffer)*
20
pF
F
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
