CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port
Static RAM
Features
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16K × 18 organization (CY7C036AV)
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0.35 micron CMOS for optimum speed and power
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High speed access: 20 and 25 ns
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Low operating power
❐ Active: ICC = 115 mA (typical)
❐ Standby: ISB3 = 10 μA (typical)
Pin select for Master or Slave (M/S)
Commercial and industrial temperature ranges
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Separate upper byte and lower byte control
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4 or 8K × 18 organization (CY7C0241AV/0251AV)
INT flag for port-to-port communication
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Semaphores included to permit software handshaking
between ports
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(CY7C024AV/024BV [1]/ 025AV/026AV)
On chip arbitration logic
Available in 100-pin Pb-free TQFP and 100-pin TQFP
4, 8 or 16K × 16 organization
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Expandable data bus to 32 bits, 36 bits or more using Master
and Slave chip select when using more than one device
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Automatic power down
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True dual-ported memory cells which enable simultaneous
access of the same memory location
Fully asynchronous operation
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CEL
CER
LBL
LBR
OEL
OER
[2]
IO8/9L–IO15/17L
[3]
IO0L–IO7/8L
8/9
8/9
12/13/14
IO
Control
A0L–A11/1213L
Address
Decode
[4]
8/9
IO
Control
True Dual-Ported
RAM Array
IO8/9L–IO15/17R
[3]
IO0L–IO7/8R
Address
Decode
12/13/14
[4]
[2]
8/9
12/13/14
[4]
A0R–A11/12/13R
[4]
12/13/14
A0L–A11/12/13L
CEL
OEL
R/WL
SEML [5]
A0R–A11/12/13R
CER
OER
R/WR
SEMR
Interrupt
Semaphore
Arbitration
[5]
BUSYL
INTL
UBL
LBL
BUSYR
INTR
UBR
LBR
M/S
Notes
1. CY7C024AV and CY7C024BV are functionally identical.
2. IO8–IO15 for x16 devices; IO9–IO17 for x18 devices.
3. IO0–IO7 for x16 devices; IO0–IO8 for x18 devices.
4. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
5. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06052 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 10, 2008
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