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74HCT373N
HD74HCT373/HD74HCT533 Octal D-type Transparent Latches (with 3-state outputs)/ Octal D-type Transparent Latches (with inverted 3-state outputs) ADE-205-555 (Z) 1st. Edition Sep. 2000 Description When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals present at the other inputs and the state of the storage elements. Features • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (Data to Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Output Control Enable G D HD74HCT373 Q HD74HCT533 Q L H H H L L H L L H L L X No change No change H X X Z Z X : Z : Irrelevant Off (high-impedance) state of a 3-state output.
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