a
Single-Chip, DSP-Based
High Performance Motor Controller
ADMC401
Internal or External Voltage Reference
Out-of-Range Detection
Voltage Reference
Internal 2.0 V ؎ 2.0% Voltage Reference
Three-Phase 16-Bit PWM Generation Unit
Programmable Switching Frequency, Dead Time and
Minimum Pulsewidth
Edge Resolution of 38.5 ns
One or Two Updates per Switching Period
Hardware Polarity Control
Individual Enable/Disable of Each Output
High Frequency Chopping Mode
Dedicated Shutdown Pin (PWMTRIP)
Additional Shutdown Pins in I/O System
High Output Sink and Source Capability (10 mA)
Incremental Encoder Interface Unit
Quadrature Rates to 17.3 MHz
Programmable Filtering of Encoder Inputs
Alternative Frequency and Direction Mode
Two Registration Inputs to Latch Count Value
Optional Hardware Reset of Counter
Single North Marker Mode
Count Error Monitor Function
Dedicated 16-Bit Loop Timer (Periodic Interrupts)
Companion Encoder Event (1/T) Timer
FEATURES
26 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (38.5 ns)
ADSP-21xx Family Code Compatible
16-Bit Arithmetic and Logic Unit (ALU)
Single Cycle 16-Bit ؋ 16-Bit Multiply and Accumulate
Into 40-Bit Accumulator (MAC)
32-Bit Shifter (Logical and Arithmetic)
Multifunction Instructions
Single Cycle Context Switch
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
2K ؋ 24-Bit Internal Program Memory RAM
2K ؋ 24-Bit Internal Program Memory ROM
1K ؋ 16-Bit Internal Data Memory RAM
14-Bit Address Bus and 24-Bit Data Bus for External
Memory Expansion
High Resolution Multichannel ADC
12-Bit Pipeline Flash Analog-to-Digital Converter
Eight Dedicated Analog Inputs
Simultaneous Sampling Capability
All Eight Inputs Converted in <2 s
4.0 V p-p Input Voltage Range
PWM Synchronized or External Convert Start
(Continued on Page 14)
FUNCTIONAL BLOCK DIAGRAM
26 MIPS DSP CORE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PM
ROM
2K ؋ 24
PM
RAM
2K ؋ 24
PROGRAM
SEQUENCER
MEMORY
DM
RAM
1K ؋ 16
EXTERNAL
ADDRESS
BUS
WATCHDOG
TIMER
POWERON
RESET
INTERRUPT
CONTROLLER
ENCODER
INTERFACE
EVENT
CAPTURE
UNIT
DIGITAL
I/O
UNIT
PROGRAM MEMORY ADDRESS
EXTERNAL
DATA
BUS
MOTOR CONTROL
PERIPHERALS
PROGRAM MEMORY DATA
DATA MEMORY ADDRESS
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
INTERVAL
TIMER
2 CHANNEL
AUXILIARY
PWM
8 CHANNEL
12-BIT ADC
PRECISION
VOLTAGE
REFERENCE
16-BIT
PWM
GENERATION
REV. B
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© Analog Devices, Inc., 2000
