September 2001
AS7C1024
AS7C31024
®
5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)
Features
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
• AS7C1024 (5V version)
• AS7C31024 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP 1
- 12/15/20 ns address access time
- 6, 7,8 ns output enable access time
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Low power consumption: ACTIVE
- 825 mW (c) / max @ 12 ns
- 360 mW (AS7C31024) / max @ 12 ns
• Low power consumption: STANDBY
Pin arrangement
- 55 mW (AS7C1024) / max CMOS
- 36 mW (AS7C31024) / max CMOS
32-pin (8 x 20mm) TSOP 1
32-pin (8 x 13.4mm) sTSOP 1
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
VCC
GND
I/O7
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O0
Control
circuit
A9
A10
A11
A12
A13
A14
A15
A16
Column decoder
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
WE
OE
CE1
CE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AS7C1024
AS7C31024
512×256×8
Array
(1,048,576)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
Row decoder
Input buffer
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AS7C1024
AS7C31024
Logic block diagram
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
9/19/01;v.1.4
AS7C1024
AS7C31024
AS7C1024
AS7C31024
-12
12
6
140
90
10
10
Alliance Semiconductor
-15
15
7
125
80
10
10
-20
20
8
110
75
15
15
Unit
ns
ns
mA
mA
mA
mA
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
