CL-CD1283
Data Book
FEATURES
Parallel Port (Peripheral-side)
High-speed, bidirectional, multi-protocol parallel port:
s Hardware implementation of all modes of the IEEE
STD (Standard) 1284 specification (including
automatic negotiation)
Centronics®-compatible mode
Reverse Byte mode
Reverse Nibble mode
ECP (extended capabilities port) mode with run-length
encoding/decoding
— EPP (enhanced parallel port) mode
— Up to 2-Mbytes/sec. transfer rate in ECP and EPP
modes
—
—
—
—
s 64-byte parallel FIFO with DMA interface
— 64-byte FIFO can accommodate up to 4 Kbytes of compressed data with RLE (run-length encoded)
compression enabled
s Supports peripheral-side operation
s Data and control input/output pads support IEEE
STD1284 level-2 interface specification
s CPU bus interface
— High-speed slave DMA handshake interface
— Three clocks per word DMA transfers
— On-the-fly data compression using RLE (run-length
encoded) encoding and decoding
— 8/16-bit data interface
IEEE 1284-Compatible
Parallel Interface Controller
OVERVIEW
The CL-CD1283 is a multi-function interface controller for printers, scanners, tape-drives, set-top boxes,
data acquisition, and other applications that require
high-speed, bidirectional, parallel communication
with a host computer. All modes of the IEEE STD
1284 Standard Signaling Method for Bidirectional
Parallel Peripheral Interface for Personal Computers specification are supported, including ECP, EPP,
Reverse Byte, Reverse Nibble, and Compatible.
With full support of this standard, the CL-CD1283
provides compatibility with all types of host parallel
ports, including older Centronics®, IBM® PS/2®
bidirectional, and the latest IEEE 1284-compliant
ports.
The dedicated state-machine design provides the
fastest possible response times to all host signal
changes, with 100% guaranteed compliance to all
IEEE 1284 timing, protocol, and signaling
(cont.)
(cont.)
Functional Block Diagram
GENERAL-PURPOSE
I/O PORT
DMA
LOGIC
COMPRESSION/
DECOMPRESSION
LOGIC
64 BYTES
INTERRUPT
LOGIC
HOST INTERFACE
Version 2.0
DATA
MOVER
LOGIC
DATA PIPELINE
FIFO
CONTROL
STATE
MACHINE
LEVEL-2
ELECTRICAL
INTERFACE
IEEE 1284 PERIPHERAL
PARALLEL PORT
October 1996
