CL-CD2401
Data Book
FEATURES
s Four full-duplex multi-protocol channels, each running
up to 134.4 kbits/sec. (@ CLK = 35 MHz)
s Supports async, HDLC/SDLC (synchronous data link
control; non-multidrop applications), bisync and X.21
on all channels
s 32-bit address, 16-bit data, double-buffered DMA controller for each transmitter and receiver; two
independent bit-rate generators per channel for transmit and receive
s On-chip NRZ (nonreturn-to-zero), NRZI (nonreturn-tozero inverted), and Manchester data encoding and
decoding
s DPLL (digital phase-locked loop) on each receiver
s Two independent timers per channel
HDLC/SDLC (Non-Multidrop) Features
s Four 8-bit or two 16-bit frame address matching
s FCS generation and validation
s CRC (cyclic redundancy check) optionally readable
s Programmable leading-pad character transmission
s Supports shared flags on receive frames
s Programmable number of leading flags
Asynchronous Features
s User-programmable and automatic flow control modes
— In-band (software) by XON/XOFF
— Out-of-band (hardware flow control) by RTS/CTS and
DTR/DSR
(cont.)
Multi-Protocol
Communications Controller
OVERVIEW
The CL-CD2401 is a four-channel synchronous/asynchronous communications controller, specifically
designed to reduce host-system processing overhead
and increase efficiency in a wide variety of communications applications. The CL-CD2401 is available in a
100-pin PQFP package that offers eight clock/modem
pins per channel. The device has four fully-independent
serial channels that support asynchronous, bit-synchronous (HDLC/SDLC), bisync (byte-synchronous), and
X.21 protocols.
The CL-CD2401 is based on a proprietary, on-chip RISC
processor that performs all the time-critical, low-level
tasks that are otherwise normally performed by the host
system.
The CL-CD2401 boosts system efficiency with on-chip
DMA, on-chip FIFOs, intelligent vectored interrupts, and
intelligent protocol processing. The on-chip DMA controller provides ‘fire-and-forget’ transmit support — the host
need only inform the CL-CD2401 of the location of the
packet to be sent. Similarly, on receive, the CL-CD2401
automatically receives a complete packet with no host
(cont.)
Functional
Block Diagram
MODEM
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
HOST
BUS
INTERFACE
LOGIC
RAM
HOST
INTERFACE
ON-CHIP
DMA
CONTROLLER
AND
INTERFACE
LOGIC
FIRMWARE
ROM
PROPRIETARY
RISC
PROCESSOR
4 SERIAL
INTERFACE
CHANNELS
MODEM
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
MODEM
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
MODEM
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
Version 7.0
August 1996
World Wide Web: http://www.cirrus.com ftp: ftp.cirrus.com/~ftp/pub/support/sio
