CY7C09269V/79V/89V
CY7C09369V/89V
3.3 V 16 K / 32 K / 64 K × 16 / 18
Synchronous Dual-Port Static RAM
3.3 V 16 K / 32 K / 64 K × 16 / 18 Synchronous Dual-Port Static RAM
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Six flow through/pipelined devices:
❐ 16 K × 16 / 18 organization (CY7C09269V/369V)
❐ 32 K × 16 organization (CY7C09279V)
❐ 64 K × 16 / 18 organization (CY7C09289V/389V)
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Three modes:
❐ Flow through
❐ Pipelined
❐ Burst
3.3 V low operating power:
❐ Active = 115 mA (typical)
❐ Standby = 10 A (typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally:
❐ Shorten cycle times
❐ Minimize bus noise
❐ Supported in flow through and pipelined modes
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True dual-ported memory cells that allow simultaneous access
of the same memory location
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High speed clock to data access: 7.5[1], 9, 12 ns (max)
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Features
Dual chip enables easy depth expansion
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Upper and lower byte controls for bus matching
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Pipelined output mode on both ports allows fast 100 MHz
operation
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Automatic power down
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0.35 micron CMOS for optimum speed and power
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Commercial and industrial temperature ranges
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Pb-free 100-pin TQFP package available
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
LBL
1
CE0R
CE1R
LBR
1
0
0
0/1
0/1
OEL
OER
1b 0b 1a 0a
0/1
FT/PipeL
[2]
b
0a 1a 0b 1b
a
a
b
0/1
8/9
FT/PipeR
8/9
I/O8/9L–I/O15/17L
[3]
I/O
Control
8/9
I/O
Control
8/9
I/O0L–I/O7/8L
[4]
A0L–A13/14/15L
CLKL
ADSL
CNTENL
CNTRSTL
[2]
I/O8/9R–I/O15/17R
[3]
I/O0R–I/O7/8R
14/15/16
14/15/16
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
[4]
A0R–A13/14/15R
CLKR
ADSR
CNTENR
CNTRSTR
Notes
1. See page 6 for Load Conditions.
2. I/O8–I/O15 for × 16 devices; I/O9–I/O17 for × 18 devices.
3. I/O0–I/O7 for × 16 devices. I/O0–I/O8 for × 18 devices.
4. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.
Cypress Semiconductor Corporation
Document #: 38-06056 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 12, 2011
