Freescale Semiconductor
Technical Data
DSP56303
Rev. 11, 2/2005
DSP56303
24-Bit Digital Signal Processor
16
6
6
3
Memory Expansion Area
Peripheral
Expansion Area
PrograM
RAM
4096 × 24
bits
(default)
Address
Generation
Unit
Six-Channel
DMA Unit
X Data
RAM
2048 × 24
bits
(default)
YAB
XAB
PAB
DAB
Y Data
RAM
2048 × 24
bits
(default)
YM_EB
SCI
XM_EB
ESSI
PM_EB
HI08
PIO_EB
Triple
Timer
18
External
Address
Bus
Address
Switch
External
Bus
13
Interface
and Inst.
Cache Control
Control
24-Bit
Bootstrap
ROM
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Internal
Data
Bus
Switch
External
Data Bus
Switch
EXTAL
XTAL
Clock
Generator
PLL
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
The DSP56303 is intended
for use in telecommunication
applications, such as multiline voice/data/ fax
processing, video
conferencing, audio
applications, control, and
general digital signal
processing.
Data ALU
24 × 24 + 56 →56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Management
24
What’s New?
Data
5
Rev. 11 includes the following
changes:
• Adds lead-free packaging and
part numbers.
JTAG
OnCE™
DE
2
RESET
PINIT/NMI
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Figure 1. DSP56303 Block Diagram
The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural
features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The
DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family
offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable
wireless, telecommunications, and multimedia products.
© Freescale Semiconductor, Inc., 1996, 2005. All rights reserved.
