.
Preliminary
IBM041841WLAD
IBM043641WLAD
128K x 36 & 256K x 18 SRAM
Features
• 128K x 36 or 256K x 18 Organizations
• CMOS Technology
• Synchronous Pipeline Mode Of Operation with
Self-Timed Late Write
• Single Ended Pseudo-PECL Clock compatible
with LVTTL Levels
• Single +3.3V Power Supply, VDDQ & Ground
• Registered Addresses, Write Enables, Synchronous Select and Data Ins
• Registered Outputs
• Asynchronous Output Enable and Power Down
Inputs
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write Capability & Global Write Enable
• Common I/O & LVTTL I/O Compatible
• Nominal 45 ohm driver
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
Scan Order.
Description
The IBM041841WLAD and IBM043641WLAD 4Mb
SRAMS are Synchronous Pipeline Mode, high performance CMOS Static Random Access Memories
that are versatile, wide I/O, and achieve 3.3ns cycle
times. A single ended K clock with K tied to 1.25V
are used to initiate the read/write operation, and all
internal operations are self-timed. At the rising edge
of the K Clock, all Addresses, Write-Enables, Sync
03K4296.E35613
Revised 02/99
Select and Data Ins are registered internally. Data
Outs are updated from output registers off the next
rising edge of the K Clock. An internal write buffer
allows write data to follow one cycle after addresses
and controls. The chip is operated with a +3.3V
power supply, output power supply compatible with
2.5V or 3.3V, and is compatible with LVTTL I/O
interfaces.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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