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IDT7027L25PF
HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25ns (max.) Low-power operation – IDT7027S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7027L Active: 750mW (typ.) Standby: 1mW (typ.) Separate upper-byte and lower-byte control for bus matching capability. Dual chip enables allow for depth expansion without external logic ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT7027S/L IDT7027 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin Ceramic Pin Grid Array (PGA) Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram R/WL UBL R/ WR UBR CE0L CE1L CE0R CE1R OEL OER LBL LBR I/O8-15R I/O 8-15L I/O Control I/O 0-7L I/O Control I/O0-7R (1,2) BUSYR BUSYL A14L Address Decoder A0L 32Kx16 MEMORY ARRAY 7027 A14L A0L CE0L CE1L OEL R/WL A14R A0R A14R ARBITRATION INTERRUPT SEMAPHORE LOGIC SEM L (2) INT L Address Decoder . M/S NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). (2) A0R CE0R CE1R OER R/WR SEM R (2) INTR 3199 drw 01 JULY 2004 1 ©2004 Integrated Device Technology, Inc. DSC 3199/8
IDT
Integrated Device Technology, Inc.
U.S.A
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