K4E171611C, K4E151611C
K4E171612C, K4E151612C
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K
Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features
of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Selfrefresh operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung′ s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer,
personal computer and portable machines.
FEATURES
• Extended Data Out Mode operation
• Part Identification
(Fast Page Mode with Extended Data Out)
• 2 CAS Byte/Word Read/Write operation
- K4E171611C-J(T)(5V, 4K Ref.)
- K4E151611C-J(T) (5V, 1K Ref.)
- K4E171612C-J(T)(3.3V, 4K Ref.)
- K4E151612C-J(T)(3.3V, 1K Ref.)
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Active Power Dissipation
Unit : mW
3.3V
Speed
• Early Write or output enable controlled write
• JEDEC Standard pinout
5V
4K
1K
4K
1K
• Available in plastic SOJ 400mil and TSOP(II) packages
-45
360
540
550
825
• Single +5V±10% power supply (5V product)
-50
324
504
495
770
• Single +3.3V±0.3V power supply (3.3V product)
-60
288
468
440
715
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
VCC
K4E171611C
5V
K4E171612C
5V
K4E151612C
Refresh period
Normal
3.3V
K4E151611C
Refresh
cycle
L-ver
RAS
UCAS
LCAS
W
Control
Clocks
3.3V
4K
64ms
1K
Refresh Timer
16ms
Refresh Counter
• Performance Range
tRAC
tCAC
Lower
Data in
Buffer
128ms
Row Decoder
Refresh Control
Speed
Vcc
Vss
VBB Generator
tRC
tHPC
Remark
-45
45ns
13ns
69ns
16ns
5V/3.3V
-50
50ns
15ns
84ns
20ns
5V/3.3V
-60
60ns
17ns
104ns
25ns
A0-A11
(A0 - A9)*1
A0 - A7
(A0 - A9)*1
Memory Array
1,048,576 x16
Cells
Row Address Buffer
5V/3.3V
Col. Address Buffer
Column Decoder
Note) *1 : 1K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sense Amps & I/O
Part
NO.
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
DQ8
to
DQ15
