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MC10105PBD
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple 2-3-2-Input OR/NOR Gate MC10105 The MC10105 is a triple 2–3–2 input OR/NOR gate. PD = 30 mW typ/gate (No Load) tpd = 2.0 ns typ tr, tf = 2.0 ns typ (20%–80%) L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 LOGIC DIAGRAM 4 5 FN SUFFIX PLCC CASE 775–02 3 2 9 10 11 6 DIP PIN ASSIGNMENT 7 13 14 12 15 VCC1 16 VCC2 AOUT 2 15 COUT AOUT 3 14 COUT AIN 4 13 CIN AIN 5 12 CIN BOUT 6 11 BIN BOUT 7 10 BIN VEE VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 1 8 9 BIN Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). 3/93 © Motorola, Inc. 1996 3–21 REV 5
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