MC10107
Triple 2-Input Exclusive OR/
Exclusive NOR Gate
•
•
•
The MC10107 is a triple–2 input exclusive OR/NOR gate.
PD = 40 mW typ/gate (No Load)
tpd = 2.8 ns typ
tr, tf = 2.5 ns typ (20%–80%)
http://onsemi.com
MARKING
DIAGRAMS
LOGIC DIAGRAM
4
2
5
3
9
11
7
10
14
MC10107L
AWLYYWW
1
12
15
16
CDIP–16
L SUFFIX
CASE 620
13
16
PDIP–16
P SUFFIX
CASE 648
3 = (4 • 5) + (4 • 5)
2 = (4 • 5) + (4 • 5)
MC10107P
AWLYYWW
1
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
1
PLCC–20
FN SUFFIX
CASE 775
DIP
PIN ASSIGNMENT
VCC1
1
16
VCC2
AOUT
2
15
CIN
AOUT
3
14
CIN
AIN
4
13
COUT
AIN
5
12
COUT
*NC
6
11
BOUT
BIN
7
10
BOUT
VEE
8
9
BIN
10107
AWLYYWW
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Shipping
MC10107L
CDIP–16
25 Units / Rail
MC10107P
PDIP–16
25 Units / Rail
MC10107FN
*NC = No Connection
Package
PLCC–20
46 Units / Rail
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
© Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Publication Order Number:
MC10107/D