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MC10107P
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple 2-Input Exclusive OR/ Exclusive NOR Gate MC10107 The MC10107 is a triple–2 input exclusive OR/NOR gate. PD = 40 mW typ/gate (No Load) tpd = 2.8 ns typ tr, tf = 2.5 ns typ (20%–80%) L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 LOGIC DIAGRAM 4 5 3 9 11 7 10 14 12 15 FN SUFFIX PLCC CASE 775–02 2 13 DIP PIN ASSIGNMENT VCC1 16 VCC2 2 15 CIN AOUT 3 14 CIN AIN 4 13 COUT AIN 5 12 COUT *NC 6 11 BOUT BIN 7 10 BOUT VEE VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 1 AOUT 3 = (4 • 5) + (4 • 5) 2 = (4 • 5) + (4 • 5) 8 9 BIN *NC = No Connection Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). 3/93 © Motorola, Inc. 1996 3–30 REV 5
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