MC10E016, MC100E016
5.0 V ECL 8−Bit
Synchronous Binary
Up Counter
Description
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The MC10E/100E016 is a high−speed synchronous, presettable,
cascadable 8−bit binary counter. Architecture and operation are the
same as the MC10H016 in the MECL 10H™ family, extended to
8−bits, as shown in the logic symbol.
The counter features internal feedback of TC, gated by the TCLD
(terminal count load) pin. When TCLD is LOW (or left open, in which
case it is pulled LOW by the internal pull−downs), the TC feedback is
disabled, and counting proceeds continuously, with TC going LOW to
indicate an all−one state. When TCLD is HIGH, the TC feedback
causes the counter to automatically reload upon TC = LOW, thus
functioning as a programmable counter. The Qn outputs do not need to
be terminated for the count function to operate properly. To minimize
noise and power, unused Q outputs should be left unterminated.
The 100 series contains temperature compensation.
MARKING DIAGRAM*
Features
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PLCC−28
FN SUFFIX
CASE 776
1
700 MHz Min. Count Frequency
1000 ps CLK to Q, TC
Internal TC Feedback (Gated)
8−Bit
Fully Synchronous Counting and TC Generation
Asynchronous Master Reset
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Pb−Free Packages are Available*
MCxxxE016G
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 7
1
Publication Order Number:
MC10E016/D