74ABT657
Octal transceiver with parity generator/checker; 3-state
Rev. 03 — 15 March 2010
Product data sheet
1. General description
The 74ABT657 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-state outputs
and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The
buffers have a guaranteed current sinking capability of 64 mA. The Transmit/Receive input
(pin T/R) determines the direction of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from A ports to B ports; Receive (active LOW)
enables data from B ports to A ports.
When Output Enable input (pin OE) is HIGH, both A and B ports are high-impedance. The
parity select input (pin ODD/EVEN) allows the user to generate either an odd or even
parity output, depending on the system. Pin PARITY is an output from the
generator/checker when transmitting from port A to port B (pin T/R = HIGH) and an input
when receiving from port B to port A port (pin T/R = LOW).
In transmit mode (pin T/R = HIGH) port A is polled to determine the number of HIGH
inputs on port A. Pin PARITY output goes to the logic state determined by the setting of
pin ODD/EVEN and by the number of HIGH inputs on port A. For example, if pin
ODD/EVEN is set LOW (even parity) and the number of HIGH inputs on port A is odd, pin
PARITY output goes HIGH, transmitting even parity. If the number of HIGH inputs on port
A is even, pin PARITY output goes LOW, keeping even parity.
In receive mode (pin T/R = LOW) port B is polled to determine the number of HIGH inputs
on port B. If pin ODD/EVEN is LOW (even parity) and the number of HIGH inputs on port
B is:
• Odd and pin PARITY input is HIGH, pin ERROR is HIGH, indicating no error
• Even and pin PARITY input is HIGH, pin ERROR goes LOW, indicating an error
2. Features and benefits
I
I
I
I
I
I
Combinational functions in one package
Low static and dynamic power dissipation with high speed and high output drive
Output capability: +64 mA and −32 mA
Power-up 3-state
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
N HBM JESD22-A114F exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
T/R
OE
A0
A1
A2
A3
A4
A5
A6
A7
ODD/EVEN
1
24
2
23
3
22
4
21
5
20
6
17
8
16
9
15
10
14
B0
B1
B2
B3
B4
B5
B6
B7
13
11
12
PARITY
ERROR
001aae828
Fig 3.
Logic diagram
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
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