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XC9500XL High-Performance CPLD
Family Data Sheet
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DS054 (v2.5) May 22, 2009
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Product Specification
Features
•
-
-
Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
-
Pb-free available for all packages
-
Lower power operation
-
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
-
3.3V or 2.5V output capability
-
Advanced 0.35 micron feature size CMOS
FastFLASH technology
Individual output enable per output pin with local
inversion
-
5 ns pin-to-pin logic delays, with internal system
frequency up to 208 MHz
-
•
-
Optimized for high-performance 3.3V systems
Local clock inversion with three global and one
product-term clocks
Input hysteresis on all user and boundary-scan pin
inputs
-
Supports hot-plugging capability
•
Bus-hold circuitry on all user pin inputs
-
Full IEEE Std 1149.1 boundary-scan (JTAG)
support on all devices
Four pin-compatible device densities
-
36 to 288 macrocells, with 800 to 6400 usable
gates
•
Fast concurrent programming
•
Advanced system features
Slew rate control on individual outputs
•
Enhanced data security features
•
Excellent quality and reliability
-
In-system programmable
-
Superior pin-locking and routability with
FastCONNECT II switch matrix
-
Extra wide 54-input Function Blocks
-
10,000 program/erase cycles endurance rating
-
Up to 90 product-terms per macrocell with
individual product-term allocation
-
20 year data retention
•
Pin-compatible with 5V core XC9500 family in common
package footprints
Table 1: XC9500XL Device Family
XC9536XL
XC9572XL
XC95144XL
XC95288XL
Macrocells
36
72
144
288
Usable Gates
800
1,600
3,200
6,400
Registers
36
72
144
288
TPD (ns)
5
5
5
6
TSU (ns)
3.7
3.7
3.7
4.0
TCO (ns)
3.5
3.5
3.5
3.8
fSYSTEM (MHz)
178
178
178
208
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countries. All other trademarks are the property of their respective owners.
DS054 (v2.5) May 22, 2009
Product Specification
www.xilinx.com
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