Si5351A/B/C
I 2 C - P R O GRA MM A B LE A NY - F R E Q U E N C Y CMOS C L O C K
G ENERATOR + VCXO
Features
Generates up to 8 non-integer-related
frequencies from 8 kHz to 160 MHz
2C user definable configuration
I
Exact frequency synthesis at each output
(0 ppm error)
Highly linear VCXO
Optional clock input (CLKIN)
Low output period jitter: 100 ps pp
Configurable spread spectrum selectable
at each output
Operates from a low-cost, fixed frequency
crystal: 25 or 27 MHz
Supports static phase offset
Programmable rise/fall time control
Glitchless frequency changes
Separate voltage supply pins:
Core VDD: 2.5 V or 3.3 V
Output VDDO: 2.5 V or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
Adjustable output-output delay
Available in 3 packages types:
10-MSOP: 3 outputs
24-QSOP: 8 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
10-MSOP
24-QSOP
Applications
20-QFN
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
Ordering Information:
See page 66
The Si5351 is an I2C configurable clock generator that is ideally suited for replacing
crystals, crystal oscillators, VCXOs, phase-locked loops (PL), and fanout buffers in costsensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional
divider architecture, the Si5351 can generate any frequency up to 160 MHz on each of its
outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide
variety of applications. The Si5351A generates up to 8 free-running clocks using an
internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an
internal VCXO and provides the flexibility to replace both free-running clocks and
synchronous clocks. The Si5351B eliminates the need for higher cost, custom pullable
crystals while providing reliable operation over a wide tuning range. The Si5351C offers
the same flexibility but synchronizes to an external reference clock (CLKIN).
Functional Block Diagram
XA
PLLA
PLL
XB
PLLB
VC
SSEN
OEB
VCXO
OSC
Multi
Synth
1
Multi
Synth
2
XB
CLKIN
PLLB
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
4
Multi
Synth
5
Si5351A
N = 2 or 7
Multi
Synth
5
Multi
Synth
6
2
IC
SSEN
OEB
Rev. 0.9 5/11
PLLA
Multi
Synth
3
Multi
Synth
N
I2C
XA
Multi
Synth
0
OSC
Multi
Synth
1
OSC
XB
XA
Multi
Synth
0
Multi
Synth
7
Si5351B
Multi
Synth
6
2
IC
INTR
OEB
Copyright © 2011 by Silicon Laboratories
Multi
Synth
7
Si5351C
Si5351A/B/C
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
