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TS555IN
TS555 Low-power single CMOS timer Datasheet - production data Features • Very low power consumption: – 110 µA typ at VCC = 5 V – 90 µa typ at VCC = 3 V N DIP8 (plastic package) • High maximum astable frequency of 2.7 MHz • Pin-to-pin functionally-compatible with bipolar NE555 • Wide voltage range: +2 V to +16 V • Supply current spikes reduced during output transitions • High input impedance: 1012 Ω D SO8 (plastic micropackage) • Output compatible with TTL, CMOS and logic MOS Description The TS555 is a single CMOS timer with very low consumption: P TSSOP8 (thin shrink small outline package) (Icc(TYP) TS555 = 110 µA at VCC = +5 V versus Icc(TYP) NE555 = 3 mA), and high frequency: (ff(max.) TS555 = 2.7 MHz versus f(max) NE555 = 0.1 MHz). Pin connections (top view) Timing remains accurate in both monostable and astable mode. The TS555 provides reduced supply current spikes during output transitions, which enable the use of lower decoupling capacitors compared to those required by bipolar NE555. With the high input impedance (1012Ω), timing capacitors can also be minimized. August 2014 This is information on a product in full production. DocID4077 Rev 3 1/21 www.st.com
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