FUNCTIONAL BLOCK DIAGRAM
COMP
PARALLEL
AVCC
AD8195
VTTI
IP[3:0]
IN[3:0]
AMUXVCC
AVEE
CONTROL
LOGIC
+
4
–
4
VTTO
4
BUFFER
EQ
PE
HIGH SPEED
+
4
–
OP[3:0]
ON[3:0]
BUFFERED
VREF_IN
VREF_OUT
SCL_IN
SDA_IN
2
SCL_OUT
SDA_OUT
2
CEC_IN
CEC_OUT
LOW SPEED
BUFFERED
07049-001
1 input, 1 output HDMI/DVI link
Enables HDMI 1.3a-compliant front panel input
4 TMDS channels per link
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs for operation with long HDMI cables
(20 m at 2.25 Gbps)
Preemphasized outputs
Fully buffered unidirectional inputs/outputs
50 Ω on-chip terminations
Low added jitter
Transmitter disable feature
Reduces power dissipation
Disables input termination
3 auxiliary buffered channels per link
Bidirectional buffered DDC lines (SDA and SCL)
Bidirectional buffered CEC line with integrated pull-up
resistors (27 kΩ)
Independently powered from 5 V of HDMI input
connector
Logic level translation (3.3 V, 5 V)
Input/output capacitance isolation
Standards compatible: HDMI, DVI, HDCP, DDC, CEC
40-lead LFCSP_VQ package (6 mm × 6 mm)
PE_EN
FEATURES
TX_EN
Data Sheet
HDMI/DVI Buffer with Equalization
AD8195
BIDIRECTIONAL
Figure 1.
TYPICAL APPLICATION
HDTV SET
MEDIA CENTER
GAME
CONSOLE
HDMI
RECEIVER
APPLICATIONS
SET-TOP BOX
Front panel buffer for advanced television (HDTV) sets
4:1 HDMI
SWITCH
AD8195
The AD8195 is an HDMI/DVI buffer featuring equalized TMDS
inputs and preemphasized TMDS outputs, ideal for systems with
long cable runs. The AD8195 includes bidirectional buffering
for the DDC bus and bidirectional buffering with integrated
pull-up resistors for the CEC bus. The DDC and CEC buffers
are powered independently of the TMDS buffers so that DDC/
CEC functionality can be maintained when the system is powered
off. The AD8195 meets all the requirements for sink tests as
defined in Section 8 of the HDMI Compliance Test 1.3c.
The AD8195 is specified to operate over the −40°C to +85°C
temperature range.
BACK PANEL
CONNECTORS
FRONT PANEL
CONNECTOR
07049-002
DVD PLAYER
GENERAL DESCRIPTION
Figure 2. Typical AD8195 Application for HDTV Sets
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Enables a fully HDMI 1.3a-compliant front panel input.
Supports data rates of up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats and greater than UXGA
(1600 × 1200) DVI resolutions.
Input cable equalizer enables use of long cables; more than
20 meters (24 AWG) at data rates of up to 2.25 Gbps.
Auxiliary buffer isolates and buffers the DDC bus and CEC
line for a single chip, fully HDMI 1.3a-compliant solution.
Auxiliary buffer is powered independently from the TMDS
link so that DDC/CEC functionality can be maintained
when the system is powered off.
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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