8101/8104 Gigabit
Ethernet Controller
Datasheet
The 8101/8104 Gigabit Ethernet Controller is a complete media access
controller (MAC sublayer) with integrated coding logic for fiber and short
haul copper media (8-bit/10-bit Physical Coding Sublayer) (8B/10B PCS)
for 1000 Mbit/s Gigabit Ethernet systems.
The 8104 is functionally the same as the 8101 except that the 8104 is in
a 208-pin Ball Grid Array (BGA) package and the 8101 is in a 208-pin
Plastic Quad Flat Pack (PQFP) package.
The Controller consists of a 32-bit system interface, receive/transmit First
In First Out (FIFO) buffers, a full-duplex Ethernet Media Access
Controller (MAC), an 8B/10B PCS, a 10-bit Physical Layer Device (PHY)
interface, and a 16-bit register interface. The controller also contains all
the necessary circuitry to implement the IEEE 802.3x Flow Control
Algorithm. Flow control messages can be sent automatically without host
intervention. Figure 1 is a block diagram of the controller.
The controller contains 53 counters which satisfy the management
objectives of the Remote Monitoring (RMON) Statistics Group MIB,
(RFC 1757), Simple Network Management Protocol (SNMP) Interfaces
Group (RFC 1213 and 1573), Ethernet-like Group MIB (RFC 1643), and
Ethernet MIB (IEEE 802.3z Clause 30). The controller also contains
136 internal 16-bit registers that can be accessed through the register
interface. These registers contain configuration inputs, status outputs,
and management counter results.
The 8101/8104 is ideal as an Ethernet controller for Gigabit Ethernet
switch ports, uplinks, backbones, and adapter cards.
November 2001
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
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