MOTOROLA
Order this document
by MCM56824A/D
SEMICONDUCTOR TECHNICAL DATA
MCM56824A
DSPRAM™
8K x 24 Bit Fast Static RAM
Single 5 V ± 10% Power Supply
Fast Access and Cycle Times: 20/25/35 ns Max
Fully Static Read and Write Operations
Equal Address and Chip Enable Access Times
Single Bit On–Chip Address Multiplexer
Active High and Active Low Chip Enable Inputs
Output Enable Controlled Three State Outputs
High Board Density PLCC Package
Low Power Standby Mode
Fully TTL Compatible
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
PIN NAMES
B
PIN ASSIGNMENTS
PLCC
7 6 5 4 3 2 1 52 51 50 49 48 47
46
8
45
9
44
10
43
11
42
12
41
13
40
14
39
15
38
16
37
17
36
18
35
19
20 21 22 23 24 25 26 27 28 29 30 31 32 3334
A
A0 – A11 . . . . . . . . . . . . . . . Address Inputs
A12, X/Y . . . . . . . . . . Multiplexed Address
V/S . . . . . . . . . Address Multiplexer Control
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
E1, E2 . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ23 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . +5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . No Connection
9 x 10 GRID
86 BUMP PBGA
CASE 896A–01
For proper operation of the device, all VSS
pins must be connected to ground.
10
C
D
E
F
G
H
J
DSPRAM is a trademark of Motorola, Inc.
REV 2
4/95
© Motorola, Inc. 1995
MOTOROLA FAST SRAM
DQ23
DQ22
DQ21
VSS
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
VSS
DQ14
DQ13
DQ11
A9
A8
A7
A6
G
VCC
VSS
E1
E2
W
NC
DQ12
•
•
•
•
•
•
•
•
•
•
FN PACKAGE
52–LEAD PLCC
CASE 778–02
A10
A11
A12
X/Y
V/S
NC
V CC
A0
A1
A2
A3
A4
A5
The MCM56824A is a 196,608 bit static random access memory organized as
8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple
chip enable inputs, output enable, and an externally controlled single address pin
multiplexer. These functions allow for direct connection to the Motorola
DSP56001 Digital Signal Processor and provide a very efficient means for implementation of a reduced parts count system requiring no additional interface logic.
The availability of multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when multiple devices are used. With
either chip enable input unasserted, the device will enter standby mode, useful
in low–power applications. A single on–chip multiplexer selects A12 or X/Y as the
highest order address input depending upon the state of the V/S control input.
This feature allows one physical static RAM component to efficiently store program and vector or scalar operands by dynamically re–partitioning the RAM
array. Typical applications will logically map vector operands into upper memory
with scalar operands being stored in lower memory. By connecting
DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control
pin, such partitioning can occur with no additional components. This allows efficient utilization of the RAM resource irrespective of operand
DQ0
type. See application diagrams at the end of this document for additionDQ1
al information.
DQ2
Multiple power and ground pins have been utilized to minimize effects
VSS
induced by output noise.
DQ3
The MCM56824A is available in a 52 pin plastic leaded chip–carrier
DQ4
(PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA.
DQ5
VIEW OF PBGA PACKAGE BOTTOM
9
8
7
6
5
4
3
2
D13 VSS
D16 D17 D18 D20 D21 D23
W
D12 D14
D15
E1
VSS
1
D19 VSS D22 A5
A4
E2
A3
A2
VSS
A1
A0
VCC
VCC
G
A6
V/S NC
A7
A8
A12 X/Y
A9
D11
D9
D10 VSS
D7
D4
D8
D6
VSS
D1
A10 A11
D5
D3
D2
D0
Not to Scale
MCM56824A
1
