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68LS373N

製品説明
仕様・特性

DM54LS373 DM74LS373 DM54LS374 DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description Features These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components They are particularly attractive for implementing buffer registers I O ports bidirectional bus drivers and working registers (Continued) Y Y Y Y Y Choice of 8 latches or 8 D-type flip-flops in a single package TRI-STATE bus-driving outputs Full parallel-access for loading Buffered control inputs P-N-P inputs reduce D-C loading on data lines Connection Diagrams Dual-In-Line Packages ’LS373 Order Number DM54LS373J DM54LS373W DM74LS373N or DM74LS373WM See NS Package Number J20A M20B N20A or W20A TL F 6431 – 1 ’LS374 Order Number DM54LS374J DM54LS374W DM74LS374WM or DM74LS374N See NS Package Number J20A M20B N20A or W20A TL F 6431 – 2 TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 6431 RRD-B30M105 Printed in U S A DM54LS373 DM74LS373 DM54LS374 DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops May 1992 Absolute Maximum Ratings (See Note) Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Input Voltage Storage Temperature Range 7V 7V b 65 C to a 150 C Operating Free Air Temperature Range b 55 C to a 125 C DM54LS DM74LS 0 C to a 70 C Recommended Operating Conditions Symbol DM54LS373 Parameter DM74LS373 Units Min Nom Max Min Nom Max 45 5 55 4 75 5 5 25 VCC Supply Voltage VIH High Level Input Votage VIL Low Level Input Voltage 07 08 V IOH High Level Output Current b1 b2 6 mA IOL Low Level Output Current 24 mA tW Pulse Width (Note 2) 15 Enable Low 15 V V 12 15 15 Data Setup Time (Notes 1 tH Data Hold Time (Notes 1 5v ns 5v 20v 20v 2) 2) Free Air Operating Temperature Note 1 The symbol ( 2 Enable High tSU TA 2 b 55 125 ns ns 0 70 C v) indicates the falling edge of the clock pulse is used for reference Note 2 TA e 25 C and VCC e 5V ’LS373 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage High Level Output Voltage VCC e Min IOH e Max VIL e Max VIH e Min Typ (Note 1) VOL Low Level Output Voltage DM54 V 34 24 Units 31 V DM74 VCC e Min IOL e Max VIL e Max VIH e Min DM54 0 25 04 0 35 DM74 IOL e 12 mA VCC e Min 05 DM74 V 04 II Input Current Input Voltage IIH High Level Input Current VCC e Max VI e 2 7V 20 mA IIL Low Level Input Current VCC e Max VI e 0 4V b0 4 mA IOZH Off-State Output Current with High Level Output Voltage Applied VCC e Max VO e 2 7V VIH e Min VIL e Max 20 mA Off-State Output Current with Low Level Output Voltage Applied VCC e Max VO e 0 4V VIH e Min VIL e Max b 20 mA Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max OC e 4 5V Dn Enable e GND IOZL IOS ICC Max 24 Max b1 5 VCC e Min II e b18 mA VOH Min VCC e Max VI e 7V 01 DM54 b 100 DM74 3 b 20 b 50 mA b 225 24 40 mA mA

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