HOME＞在庫検索＞在庫情報
74HC165N
MM54HC165 MM74HC165 Parallel-in Serial-out 8-Bit Shift Register General Description The MM54HC165 MM74HC165 high speed PARALLEL-IN SERIAL-OUT SHIFT REGISTER utilizes advanced silicongate CMOS technology It has the low power consumption and high noise immunity of standard CMOS integrated circuits along with the ability to drive 10 LS-TTL loads This 8-bit serial shift register shifts data from QA to QH when clocked Parallel inputs to each stage are enabled by a low level at the SHIFT LOAD input Also included is a gated CLOCK input and a complementary output from the eighth bit Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a CLOCK INHIBIT function Holding either of the CLOCK inputs high inhibits clocking and holding either CLOCK input low with the SHIFT LOAD input high enables the other CLOCK input Data transfer occurs on the positive going edge of the clock Parallel load- Connection Diagram ing is inhibited as long as the SHIFT LOAD input is high When taken low data at the parallel inputs is loaded directly into the register independent of the state of the clock The 54HC 74HC logic family is functionally as well as pinout compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Features Y Y Y Y Y Typical propagation delay 20 ns (clock to Q) Wide operating supply voltage range 2 – 6V Low input current 1 mA maximum Low quiescent supply current 80 mA maximum (74HC Series) Fanout of 10 LS-TTL loads Function Table Inputs Internal Output Shift Clock Parallel Outputs QH Clock Serial Load Inhibit A H QA QB Dual-In-Line Package L H H H H X L L L H X L u u X X X H L X a h X X X X a QA0 H L QA0 b QB0 QAN QAN QB0 h QH0 QGN QGN QH0 H e High Level (steady state) L e Low Level (steady state) X e Irrelevant (any input including transitions) u e Transition from low to high level QA0 QB0 QH0 e The level of QA QB or QH respectively before the indicated steady-state input conditions were established QAN QGN e The level of QA or QG before the most recent the clock indicates a one-bit shift u transition of TL F 5316 – 1 Top View Order Number MM54HC165 or MM74HC165 C1995 National Semiconductor Corporation TL F 5316 RRD-B30M105 Printed in U S A MM54HC165 MM74HC165 Parallel-in Serial-out 8-Bit Shift Register January 1988 AC Electrical Characteristics VCC e 5V Symbol TA e 25 C CL e 15 pF tr e tf e 6 ns Parameter Typ Guaranteed Limit Units fMAX Maximum Operating Frequency Conditions 50 30 MHz tPHL tPLH Maximum Propagation Delay H to QH or QH 15 25 ns tPHL tPLH Maximum Propagation Delay Serial Shift Parallel Load to QH 13 25 ns tPHL tPLH Maximum Propagation Delay Clock to Output 15 25 ns tS Minimum Setup Time Serial Input to Clock Parallel or Data to Shift Load 10 20 ns tS Minimum Setup Time Shift Load to Clock 11 20 ns tS Minimum Setup Time Clock Inhibit to Clock 10 20 ns tH Minimum Hold Time Serial Input to Clock or Parallel Data to Shift Load 0 ns tW Minimum Pulse Width Clock 16 ns AC Electrical Characteristics CL e 50 pF Symbol Parameter Conditions tr e tf e 6 ns (unless otherwise specified) VCC TA e 25 C Typ 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units Guaranteed Limits fMAX Maximum Operating Frequency 2 0V 4 5V 6 0V 10 45 50 5 27 32 4 21 25 4 18 21 MHz MHz MHz tPHL tPLH Maximum Propagation Delay H to QH or QH 2 0V 4 5V 6 0V 70 21 18 150 30 26 189 38 33 225 45 39 ns ns ns tPHL tPLH Maximum Propagation Delay Serial Shift Parallel Load to QH 2 0V 4 5V 6 0V 70 21 18 175 35 30 220 44 37 260 52 44 ns ns ns tPHL tPLH Maximum Propagation Delay Clock to Output 2 0V 4 5V 6 0V 70 21 18 150 30 26 189 38 33 225 45 39 ns ns ns tS Minimum Setup Time Serial Input to Clock or Parallel Data to Shift Load 2 0V 4 5V 6 0V 35 11 9 100 20 17 125 25 21 150 30 25 ns ns ns tS Minimum Setup Time Shift Load to Clock 2 0V 4 5V 6 0V 38 12 9 100 20 17 125 25 21 150 30 25 ns ns ns tS Minimum Setup Time Clock Inhibit to Clock 2 0V 4 5V 6 0V 35 11 9 100 20 17 125 25 21 150 30 25 ns ns ns tH Minimum Hold Time Serial Input to Clock or Parallel Data to Shift Load 2 0V 4 5V 6 0V 0 0 0 0 0 0 0 0 0 ns ns ns tW Minimum Pulse Width Clock 2 0V 4 5V 6 0V 30 9 8 80 16 14 100 20 18 120 24 20 ns ns ns tTHL tTLH Maximum Output Rise and Fall Time 2 0V 4 5V 6 0V 30 9 8 75 15 13 95 19 16 110 22 19 ns ns ns tr tf Maximum Input Rise and Fall Time 2 0V 4 5V 6 0V 1000 500 400 1000 500 400 1000 500 400 ns ns ns CPD Power Dissipation Capacitance (Note 5) CIN Maximum Input Capacitance (per package) 100 5 pF 10 10 10 pF Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 3
MOT
1999年8月4日、ディスクリート・標準アナログ・標準ロジックなどの半導体部門をオン・セミコンダクターとして分社化した。これは、イリジウムコミュニケーションズ倒産の損失をカバーするために分社化された。
ON Semiconductor
U.S.A
オン・セミコンダクターの前身は、モトローラ社の半導体コンポーネント・グループであり、モトローラ社のディスクリート、標準アナログ、標準ロジック・デバイスを継続して製造。
弊社からの見積回答メールの返信又はFAXにてお願いします。
